您所在的位置: 首页» 活动资讯

【百家大讲堂】第236期:AI时代2.5/3D技术

编辑: 研究生院 发布日期: 2019-09-11 浏览量:

讲座题目:AI时代2.5/3D技术  Future 2.5/3D Technologies in AI Era

报 告 人:小柳光正 Mitsumasa Koyanagi(教授/GINTI中心主任)

时   间:2019年9月13日(周五)10:00-11:30

地   点:中关村校区信息实验楼205会议室

主办单位:研究生院、信息与电子学院

报名方式:登录北京理工大学微信企业号---第二课堂---课程报名中选择“【百家大讲堂】第236期:AI时代2.5/3D技术

【主讲人简介】

  小柳光正(Mitsumasa Koyanagi)教授1947年生于日本北海道,并于1974年获得日本东北大学博士学位。1974年至1980年于日立的中央研究实验室发明了世界上第一款商业化的三维堆叠电容型动态随机存取存储器;1985年至1988年,他加入了位于美国加州的帕罗奥多研究中心,从事亚微米CMOS器件、多晶硅薄膜晶体管等的研究;1988年,加入广岛大学,从事亚微米器件加工及表征、器件建模、多晶硅TFT器件、三维集成技术、光学互连以及并行计算系统研究,并于1992年成功制备出栅长70nm的当时最小尺寸的MOS管,相关研究发表于当年的IEDM;1989年,在国际上首次提出基于晶圆键合工艺以及穿透硅通孔技术为基础的三维集成技术并一直在该领域处于国际领先地位,所带领的课题组已经在IEDM上发表相关研究论文10余篇;在三维集成以及光学互连领域有20余年的研究经验,发表了300余篇署名期刊论文,国际会议受邀演讲达到100余次, 为IEEE协会Fellow,日本应用物理学会Fellow,先后被IEEE协会、日本应用物理协会、日本文部科学省等授予多项奖励。目前为日本东北大学教授、GINTI中心主任。

 

Mitsumasa Koyanagi (M86-M’90-F’97) was born in Hokkaido, Japan. He received the B.S. degree in electrical engineering from Muroran Institute of Technology, Muroran, Japan, in 1969 and the M.S. and Ph.D degrees in electronic engineering from Tohoku University, Sendai, Japan, in 1971 and 1974, respectively. 
 
From 1974 to 1980, he was with Central Research laboratory, Hitachi Ltd., where he invented a stacked capacitor dynamic random access memory (DRAM) memory cell, which was the first commercialized 3-D large-scale integration (LSI) system. From 1980 to 1985, he was with the Device Development Center, Hitachi Ltd. From 1985 to 1988, he joined the Xerox Palo Alto Research Center, Palo Alto, CA, where he worked on the research and development of submicrometer complementary metal-oxide-semiconductor (CMOS) devices, polysilicon thin-film transistors, and the design of analog/digital LSIs. 
 

In 1988, he joined the Research Center for Integrated Systems, Hiroshima University, Hiroshima, as a Professor, where he worked on scaled MOS devices, 3-D integration technology, optical interconnections, and parallel computer systems specific for scientific computation. He fabricated the smallest MOS transistor with a gate length of 70nm in 1992. He proposed a 3-D integration technology based on wafer-to-wafer bonding for the first time in 1989. 

 

Since 1994, he has been a Professor with Tohoku University(the Department of Machine Intelligence and Systems Engineering, the Department of Bioengineering and Robotics, and, currently, the New Industry Creation Hatchery Center), where his current interests are Nano-CMOS devices, memory devices, low-voltage and low-power integrated circuits, new intelligent memory for parallel processor systems, 3-D integration technology, optical interconnections, parallel computer systems specific for science computation, real-time image processing systems and artificial retina chips, retinal prosthesis, and brain-implant devices and brainlike computer systems. He has been researching 3-D integration technology and optical interconnection for more than 20 years.

 

Dr. Koyanagi was the receipt of the 2006 IEEE Jun-ichi Nishizawa Medal, the 1996 IEEE Cledo Brunetti Award, the 2001 Award of Ministry of Education, Culture, Sports, Science and Technology, the 1994 Solid-State Devices and Materials Award, the 2004 Optoelectronic Technology Achievement Award(Japan Society of Applied Physics), and the 1990 Okouchi Prize.

 

【讲座信息】

2.5/3D集成技术是未来适应AI时代应用的高性能、低功耗、多功能超大规模集成电路与系统关键技术之一。特别是随着晶体管尺寸进一步缩小至10nm以下带来的诸如器件设计/制造成本攀升、互连延迟等问题加剧,具备将在不同衬底材料上利用不同工艺节点技术制备的多种不同大小和功能的器件芯片等在同一硅晶圆上进行3D异质系统集成已逐渐成为延续摩尔定律的有效手段。本次讲座将在回顾2.5/3D集成技术发展现状基础上,结合未来AI时代应用需求对2.5/3D技术发展要求进行解析和展望。

 

2.5/3D integration technology is the key for future LSIs with high-performance, low-power and multi-functionality in the future AI era. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology will be discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.